We license under a per-tape-out plus per-unit royalty model. The per-tape-out fee covers RTL delivery, sign-off scripts, the UVM testbench, the characterisation report, and integration support for one tape-out cycle. Per-unit royalties scale with shipped volume and are tiered by node and configuration. Multi-project and unlimited-volume buy-out options are available for high-volume programmes.

Top-line specifications, performance numbers, and indicative pricing are shared without an NDA. Full datasheets, deliverables lists, characterisation reports, and reference RTL require a mutual NDA. Our standard mutual NDA is two pages and routes through legal review in 2–5 business days; we can also work under a customer-supplied NDA, with marginally longer turnaround.

For pure custom RTL and ASIC design service work, the customer owns the resulting design under a work-for-hire arrangement, with Antikode retaining ownership only of pre-existing reusable infrastructure (testbench primitives, library cells, and similar). For engagements that integrate Antikode IP, the integrated design is jointly used under the licensing terms of the underlying IP.

Existing IP licensing is delivered within 4–6 weeks of contract signing — the bulk of the time is integration support and customer-specific configuration. Custom RTL engagements typically scope at 6–14 months, depending on complexity. Full FPGA-to-ASIC migrations are 9–18 months, with the front-end portion (RTL hardening + verification) generally 4–6 months and the physical-design portion gated on PDK and customer schedule.

Production support: TSMC 28nm HPC+ and 22ULL, GlobalFoundries 22FDX. Engineering support and porting available for: TSMC 16nm FFC, GlobalFoundries 12LP+, and SMIC 28nm. We do not currently support sub-16nm nodes — we expect to add 16nm production support in 2027.

Yes. The RV-32IM core passes the full RISC-V Architecture Test Suite (RVI compatibility tests), is RVA20U64-baseline-compatible for the privileged extensions we implement, and is registered in the public RISC-V SoC directory. We are members of RISC-V International and contribute to the verification working group.

Yes. The automotive-qualified configuration of the RV-32IM is targeted at AEC-Q100 Grade 1 and ASIL-B per ISO 26262, with documented FMEDA, safety manual, and lock-step support. The first production part using this configuration is in qualification with a Korean Tier-2 supplier; expected production volumes begin mid-2027.

We are headquartered in Jakarta, with the engineering team primarily based in our Bandung office. Most customer engagements run remote with quarterly on-site reviews — we travel to the customer for major milestones, and customers visit Bandung for tape-out signoff and silicon bring-up.