Open-sourcing our UVM verification templates for RISC-V cores
After cleaning up four years of internal verification IP, we are releasing the templates we use to bring up RISC-V cores from RTL to sign-off. MIT-licensed, on GitHub today.
Author
Antikode
Verification eats more than half of every chip project we ship. The reusable parts of that effort have lived in our internal Antikode SVN repo for four years, accumulating refinements from twelve tape-outs. Today we are open-sourcing a cleaned-up version under MIT license at github.com/antikode/uvm-riscv-templates.
What is in the box: a parameterised RISC-V instruction monitor that decodes RV32IM/IMC/IMAFC, a coverage model with predefined coverpoints for ISA, micro-architectural events, and exception conditions, a memory subsystem agent supporting AHB-Lite and AXI-Lite, a constrained-random instruction stream generator that interoperates with riscv-dv, and configurable scoreboards for in-order and out-of-order architectures.
It is opinionated. It assumes UVM 1.2 or later, a SystemVerilog-compliant simulator (we test on Xcelium and Questa), and a project layout that mirrors what we use internally. It is not a turn-key verification environment — it is a starting point that gets you from "RTL exists" to "running directed tests against a working monitor" in two days instead of two weeks.
Why we are doing this
The Indonesian and Southeast Asian semiconductor design community is small but growing. The biggest gap we see is not RTL talent — it is verification methodology. Treating these templates as a competitive moat made sense in 2020. In 2026 it just slows down the ecosystem we depend on. The templates are sufficient to bring up a hobby or research RISC-V core from scratch; if you want production sign-off support, we still sell that as a service.
Issues, PRs, and feature requests welcome on the GitHub repo. The maintainers are members of our verification team, with replies typically within two business days. We will be running a hands-on workshop on the templates at the upcoming RISC-V Summit Asia in Singapore.
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