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Engineering

FPGA-to-ASIC migration: the lessons we keep relearning

Most FPGA prototypes are not ASIC-ready, no matter what the vendor synthesis report says. After 12 tape-outs, here is the short list of things that always bite — and how we now catch them in week one.

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Engineering

Open-sourcing our UVM verification templates for RISC-V cores

After cleaning up four years of internal verification IP, we are releasing the templates we use to bring up RISC-V cores from RTL to sign-off. MIT-licensed, on GitHub today.

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